In recent years, for example, a matrix converter has been known as a direct conversion circuit that does not require a direct current (DC) smoothing circuit including an electrolytic capacitor or a DC reactor in a power conversion apparatus, such as an alternating current (AC)/AC conversion apparatus, an AC/DC conversion apparatus, or a DC/AC conversion apparatus using a semiconductor element.
The matrix converter includes a plurality of AC switches. Since an AC voltage is applied to the AC switch, the AC switch requires a structure having both the forward and reverse withstand voltages (hereinafter, referred to as a forward withstand voltage and a reverse withstand voltage). Therefore, attention is paid to a bidirectional switching element in order to reduce the size, weight, and costs of a circuit and to increase efficiency and a response speed.
For example, a switch which is formed by connecting two reverse blocking insulated gate bipolar transistors (hereinafter, referred to as reverse blocking IGBTs) in inverse parallel has been known as the bidirectional switching element.
When the switching element formed by connecting the reverse blocking IGBTs in inverse parallel is used, the reverse blocking IGBT has the functions of an IGBT and a diode. When the reverse blocking IGBT is operated as the diode, an on-signal is applied to the gate of the IGBT to constantly open the channel. Then, a pn diode is formed by a p collector region, an n drift region, an n channel region, and an n emitter region of the reverse blocking IGBT.
The on-signal is applied to the gate of the reverse blocking IGBT to change the operation mode to a diode mode and a forward current flows to the diode. Excess carriers are stored in the drift region of the diode by the forward current. Thereafter, when a reverse voltage is applied to the diode, the stored excess carriers are swept and a reverse recovery current flows to generate a reverse recovery voltage. When the excess carriers are rapidly swept and the remaining carriers are reduced, the reverse recovery voltage and current oscillate. When the oscillation increases, a reverse recovery breakdown occurs. Therefore, it is preferable to reduce the oscillation.
FIG. 11 is a cross-sectional view illustrating a reverse blocking IGBT according to the related art. As illustrated in FIG. 11, in the reverse blocking IGBT, a separation portion 330 which surrounds an active region 310 is provided at the outer circumferential end of an n− semiconductor substrate. A vertical IGBT including an n− drift region 201, a p-type base region 202, an n+ emitter region 203, and a p-type collector region 210 is provided in the active region 310. For example, a p-type isolation region 231 which extends from the front surface to the rear surface of the semiconductor substrate is provided in the isolation portion 330. The isolation region 231 comes into contact with the collector region 210 provided in the rear surface of the active region 310. A withstand voltage structure region 320 is provided between the isolation portion 330 and the active region 310. The withstand voltage structure region 320 reduces the electric field intensity of the surface of a pn junction forming the semiconductor device and obtains a desired withstand voltage.
FIG. 12 is a cross-sectional view illustrating in detail the active region 310 of the reverse blocking IGBT illustrated in FIG. 11. In the active region 310, the p-type base region 202 is selectively provided in the surface of the drift region 201 which is the n− semiconductor substrate. The base region 202 has a higher impurity concentration than the drift region 201. The n+ emitter region 203 and the p+ body region 204 are selectively provided in the surface of the base region 202. A gate electrode 207 partially covers the emitter region 203 and the base region 202, with a gate insulating film 206 interposed therebetween. An emitter electrode 209 comes into contact with the emitter region 203 and the body region 204. In addition, the emitter electrode 209 is electrically insulated from the gate electrode 207 by an interlayer insulating film 208. The p-type collector region 210 and a collector electrode 211 are provided on a second main surface Y2 (rear surface) of the drift region 201.
When a silicon (Si) substrate manufactured by a floating zone (FZ) method is used, the reverse blocking IGBT can be a non-punch through (NPT) type in which a depletion layer that is spread from the emitter when the semiconductor device is turned off does not reach the collector. The reason is as follows. With the improvement of a technique for grinding the silicon substrate manufactured by the FZ method, it is possible to reduce the thickness of the silicon substrate to about 100 μm when the rated voltage of the IGBT is, for example, 600 V and to about 180 μm when the rated voltage is 1200 V. In the NPT-type IGBT, the thickness of the collector region is reduced and the impurity concentration of the collector region is reduced to decrease the injection efficiency of minority carriers from the collector region and to increase transport efficiency. As such, the NPT-type reverse blocking IGBT can solve the problems caused by the tradeoff relation between on-voltage characteristics and turn-on loss and reduce the on-voltage and the turn-on loss.
As the reverse blocking IGBT, a device has been proposed in which a p base region is formed in the surface of a semiconductor substrate, an n+ emitter region is formed in the surface of the p base region, a p+ collector region (a p+ region which is formed in a side surface and a p+ collector region which is formed in the rear surface) is formed in the outer circumferential portion and rear surface of the semiconductor substrate so as to surround the p base region, and the thickness of the p+ collector region formed in the rear surface is about 1 μm (for example, see the following Patent Document 1).
As another device, the following device has been proposed. A high-withstand-voltage semiconductor device includes a semiconductor substrate that has a single layer and at least pn junctions for forward and reverse withstand voltages which are formed on both sides of the single layer. The withstand voltage junction termination structures of the two pn junctions are provided on the first main surface side of the semiconductor substrate by an isolation region. The single layer of the semiconductor substrate includes a region having a substantially uniform impurity concentration distribution from the first main surface to the inside or having an impurity concentration distribution in which impurity concentration is reduced from the first main surface toward the inside (for example, see the following Patent Document 2).
FIG. 13 is a cross-sectional view illustrating another example of the reverse blocking IGBT according to the related art. In the reverse blocking IGBT illustrated in FIG. 13, an n-type shell region 301 is provided between a drift region 201 and a base region 202. The shell region 301 has a higher impurity concentration than the drift region 201. An n-type buffer region 302 is provided between the drift region 201 and a collector region 210. The buffer region 302 has a higher impurity concentration than the drift region 201. The other structures are the same as those in the reverse blocking IGBT illustrated in FIG. 11. As such, an IGBT has been known in which the region (the shell region 301 or the buffer region 302) which has the same conductivity type as the drift region 201 and has a higher impurity concentration than the drift region 201 is provided at the interface between the drift region 201 and the base region 202, the interface between the drift region 201 and the collector region 210, or both the interfaces, in order to improve characteristics.
As this type of IGBT, the following device has been proposed. An IGBT has regions which have different conductivity types and are alternately provided so as to overlap each other. The dimensions of the IGBT are determined such that punch-through does not occur. The IGBT includes two buffer layers. The buffer layer has the same conductivity type as the drift region and is heavily doped with impurities. In this way, a structural element is contrastively blocked. In addition, in the IGBT, the forward withstand voltage and the reverse withstand voltage can have substantially the same level (for example, see the following Patent Document 3).
As still another device, the following device has been proposed. An IGBT includes the above-mentioned buffer layers and the dimensions of the IGBT are determined such that punch-through does not occur for both forward and reverse biases. The buffer layer has the same conductivity type as a drift region and is heavily doped with impurities (for example, see the following Patent Document 4).
As yet another device, the following device has been proposed. A high-concentration region which has the same conductivity type as an n drift region and has a higher impurity concentration than the n drift region is provided at least a portion of the boundary between a p base region and the n drift region. In this way, a channel length is reduced and a voltage drop is reduced in an on state (for example, see the following Patent Document 5).
As still yet another device, the following device has been proposed. A high-concentration region which has the same conductivity type as an n drift region and has a higher impurity concentration than the n drift region is provided in the vicinity of a p base region in the n drift region. In this way, a voltage drop is reduced in an on state (for example, see the following Patent Document 6).
As yet still another device, the following device has been proposed. A short-lifetime region is formed in a portion of an n base layer close to a p collector region. The short-lifetime region is an n type and has a higher impurity concentration than the n base layer. In this way, the leakage current of an NPT-type IGBT is reduced (for example, see the following Patent Document 7).
As still yet another device, the following device has been proposed. A high-concentration region which has the same conductivity type as an n drift region and has a higher impurity concentration than the n drift region is provided in a portion of an n base layer close to a p collector region. In this way, even when a partial loss occurs in the collector region, the loss is less likely to affect an increase in voltage drop characteristics in an on state or a reduction in withstand voltage characteristics (for example, see the following Patent Document 8).
As yet still another device, an NPT-type IGBT has been proposed in which an n+ region is provided in a portion of an n− drift region close to a p base region to improve both an on-voltage and an off-voltage (forward voltage) (for example, see the following Patent Document 9).
However, the technique disclosed in the above-mentioned Patent Document 4 has the problem that the reverse leakage current is more than the forward leakage current due to the influence of the high-concentration p-type body region which is formed in the p base layer in order to improve the latch-up resistance of the IGBT.
The technique disclosed in the above-mentioned Patent Document 3 has the following problems. The problems will be described with reference to the characteristic diagram of FIG. 13 illustrating the relationship between a height y from the bottom of the substrate and electric field intensity E. In the reverse blocking IGBT illustrated in FIG. 13, since the shell region 301 and the buffer region 302 are provided, the electric field of the semiconductor substrate rapidly increases. For example, during forward bias (a solid line in FIG. 13), the electric field rapidly increases in a region in the vicinity of the interface between the base region 202 and the shell region 301. On the other hand, during reverse bias (a dotted line in FIG. 13), the electric field rapidly increases in a region in the vicinity of the interface between the collector region 210 and the buffer region 302. Therefore, in many cases, the forward withstand voltage and the reverse withstand voltage are reduced. That is, there is a concern that the forward withstand voltage and the reverse withstand voltage which are expected to be actually obtained will not be obtained by the shell region 301 and the buffer region 302.
It has been known that this problem can be solved by reducing the impurity concentration of the drift region. However, when the impurity concentration of the drift region is reduced, the depletion layer reaches the buffer region 302 during the operation of the semiconductor device, which results in a punch-through phenomenon. Therefore, a voltage waveform and a current waveform (hereinafter, referred to as a turn-on waveform) oscillate when the semiconductor device is turned on. In addition, the reverse blocking IGBT has the characteristics (reverse recovery characteristics) that a large amount of current transiently flows when the reverse blocking IGBT switches from an on state to a reverse blocking state. Therefore, the voltage waveform and the current waveform during reverse recovery (hereinafter, referred to as a reverse recovery waveform) are likely to oscillate. When the turn-on waveform and the reverse recovery waveform oscillate, noise is generated. When the oscillation of the voltage waveform is too large, there is a concern that the semiconductor device will be broken.
The technique disclosed in the above-mentioned Patent Document 3 has the problem that, since the p-type base region is formed so as to overlap the n-type shell region 201, it is difficult to control the concentration and depth of the n-type shell region 201. In addition, the above-mentioned Patent Document 3 does not disclose a deep p-type region which is generally formed at the end of the active region in order to improve turn-on resistance and is connected to the emitter electrode. In addition, there is a concern that a forming process will be complicated in order to form the n-type shell region 201 so as to cover the deep p-type region. When the n-type shell region 201 is not formed so as to cover the deep p-type region, there is a concern that a reduction in the reverse leakage current will be limited.
The above-mentioned problems also occur when the technique disclosed in the above-mentioned Patent Document 6 is applied to the reverse blocking IGBT.
The above-mentioned Patent Document 9 does not disclose the reverse blocking IGBT. Therefore, the above-mentioned Patent Document 9 does not disclose the operation of the n+ region and the reverse leakage current when the reverse voltage is applied.